Process Engineer I, II, or Senior, Texas Institute for Electronics Full-time

Process Engineer I, II, or Senior, Texas Institute for Electronics

This position may be filled at a higher-level title, relative to experience and qualifications of the selected candidate.

About Us

The Texas Institute for Electronics (TIE) is a University of Texas at Austin-supported semiconductor consortium of state and local government, preeminent defense electronics and semiconductor companies, national labs and nationally recognized academic institutions. Our mission is to develop and execute a state-of-the-art 3D Heterogenous Integration manufacturing technology roadmap, and to provide critical pilot manufacturing capabilities to address national security needs and catalyze domestic economic growth.

Join the Texas Institute for Electronics (TIE) and help us push the boundaries in critical semiconductor domains, including advanced packaging, with the aim of reestablishing U.S. prominence in semiconductor manufacturing.

With over $1 billion in funding from the US DoD and the state of Texas, we're at the forefront of creating cutting-edge semiconductor manufacturing equipment and processes that will set the course for future advancements in semiconductor logic, memory, heterogeneous integration, chip cooling and more. Situated in the heart of Austin — named “America's Coolest City” by Expedia and “The Best Place to Live in the U.S.” by U.S. News and World Report — the Texas Institute for Electronics embodies the city's innovative spirit.

UT Austin, recognized by Forbes as one of America's Best Large Employers, provides outstanding employee benefits and total rewards packages that include:

• Competitive health benefits (employee premiums covered at 100%, family premiums at 50%)
• Voluntary Vision, Dental, Life, and Disability insurance options
• Generous paid vacation, sick time, and holidays
• Teachers Retirement System of Texas, a defined benefit retirement plan, with 8.25% employer matching funds
• Additional Voluntary Retirement Programs: Tax Sheltered Annuity 403(b) and a Deferred Compensation program 457(b)
• Flexible spending account options for medical and childcare expenses
• Robust free training access through LinkedIn Learning plus professional conference opportunities
• Tuition assistance
• Expansive employee discount program including athletic tickets
• Free access to UT Austin's libraries and museums with staff ID card
• Free rides on all UT Shuttle and Austin CapMetro buses with staff ID card
• For more details, please see: Benefits | Human Resources and UT Austin Employee Experience | Human Resources

Purpose

The Process Engineer I, II, or Senior develops and executes semiconductor fabrication process flows for advanced 3D HI applications using a wide variety of internal and external fabrication resources.

Responsibilities

• Running, developing and integrating semiconductor fabrication processes across a wide variety of semiconductor equipment. This would include running experiments, performing detailed process characterization, performing data analysis, documentation of processes of record, presentation of results, and incorporating feedback from engineers/techs.
• Developing processes-of-record and implementing these on product samples for customers.
• Assisting with documents such as proposals or reports on costs and inventory levels.

Required Qualifications

Process Engineer I:

High School Diploma or GED and at least ten years of experience in materials science, physics, chemistry, chemical engineering, electrical engineering, mechanical engineering, or other relevant disciplines, or, Bachelor's degree in materials science, physics, chemistry, chemical engineering, electrical engineering, mechanical engineering, or other relevant disciplines and at least six years of relevant experience in nanofabrication and exposure to wafer processing and characterization in cleanrooms, including experience working with standard semiconductor equipment for lithography, coating, plasma processes including deposition and etch, wet cleans, electroplating, annealing, chemical mechanical polishing, bonding, packaging, metrology and inspection.

Process Engineer II:

Bachelor's degree in materials science, physics, chemistry, chemical engineering, electrical engineering, mechanical engineering, or other relevant disciplines and eight years of relevant experience in nanofabrication and exposure to wafer processing and characterization in cleanrooms, including experience working with standard semiconductor equipment for lithography, coating, plasma processes including deposition and etch, wet cleans, electroplating, annealing, chemical mechanical polishing, bonding, packaging, metrology and inspection, or, Master's degree in materials science, physics, chemistry, chemical engineering, electrical engineering, mechanical engineering, or other relevant disciplines and six years of relevant experience in nanofabrication and exposure to wafer processing and characterization in cleanrooms, including experience working with standard semiconductor equipment for lithography, coating, plasma processes including deposition and etch, wet cleans, electroplating, annealing, chemical mechanical polishing, bonding, packaging, metrology and inspection.

Senior Process Engineer:

Bachelor's degree in materials science, physics, chemistry, chemical engineering, electrical engineering, mechanical engineering, or other relevant disciplines and ten years of experience in nanofabrication and exposure to wafer processing and characterization in cleanrooms, including experience working with standard semiconductor equipment for lithography, coating, plasma processes including deposition and etch, wet cleans, electroplating, annealing, chemical mechanical polishing, bonding, packaging, metrology and inspection, or

Master's degree in materials science, physics, chemistry, chemical engineering, electrical engineering, mechanical engineering, or other relevant disciplines and eight years of relevant experience in nanofabrication and exposure to wafer processing and characterization in cleanrooms, including experience working with standard semiconductor equipment for lithography, coating, plasma processes including deposition and etch, wet cleans, electroplating, annealing, chemical mechanical polishing, bonding, packaging, metrology and inspection, or PhD in materials science, physics, chemistry, chemical engineering, electrical engineering, mechanical engineering, or another relevant discipline.

For all levels:

• Goal-oriented and ability to prioritize and multitask.
• Demonstrated excellent written and verbal communication skills.
• Demonstrated ability to work successfully in a collaborative team environment.
• Ability to work effectively in a dynamic and fast paced environment.

Relevant education and experience may be substituted as appropriate.

Preferred Qualifications

Process Engineer I:

Three years of experience in nanofabrication and exposure to wafer processing and characterization in cleanrooms, including experience working with standard semiconductor equipment for lithography, coating, plasma processes including deposition and etch, wet cleans, electroplating, annealing, chemical mechanical polishing, bonding, packaging, metrology and inspection.

Process Engineer II:

Master's degree or higher. Five or more years of relevant experience in nanofabrication and exposure to wafer processing and characterization in cleanrooms, including experience working with standard semiconductor equipment for lithography, coating, plasma processes including deposition and etch, wet cleans, electroplating, annealing, chemical mechanical polishing, bonding, packaging, metrology and inspection.

Senior Process Engineer:

Master's degree or higher. Ten or more years of experience in nanofabrication and exposure to wafer processing and characterization in cleanrooms, including experience working with standard semiconductor equipment for lithography, coating, plasma processes including deposition and etch, wet cleans, electroplating, annealing, chemical mechanical polishing, bonding, packaging, metrology and inspection.

For all levels:

• Experience working in a research or start-up environment.
• Experience with programmatic layout creation software such as KLayout.

Salary Range

TIE pays industry-competitive salaries

Working Conditions

• Work is performed on-site in a scientific research environment, with dynamic work conditions and frequent interruptions.
• Work outside standard office hours could be required on an occasional basis during peak periods and special events.
• May work around standard office conditions
• May work around chemicals
• Repetitive use of a keyboard at a workstation
• Use of manual dexterity (ex: using a mouse)
• May work in a cleanroom environment.

Required Materials

• Resume/CV
• 3 work references with their contact information; at least one reference should be from a supervisor
• Letter of interest

Important for applicants who are NOT current university employees or contingent workers: You will be prompted to submit your resume the first time you apply, then