The Process Engineer I, II, or Senior develops and executes semiconductor fabrication process flows for advanced 3D HI applications using a wide variety of internal and external fabrication resources.
The Texas Institute for Electronics (TIE) is a University of Texas at Austin-supported semiconductor consortium of state and local government, preeminent defense electronics and semiconductor companies, national labs and nationally recognized academic institutions. Our mission is to develop and execute a state-of-the-art 3D Heterogenous Integration manufacturing technology roadmap, and to provide critical pilot manufacturing capabilities to address national security needs and catalyze domestic economic growth.
Join the Texas Institute for Electronics (TIE) and help us push the boundaries in critical semiconductor domains, including advanced packaging, with the aim of reestablishing U.S. prominence in semiconductor manufacturing.
With over $1 billion in funding from the US DoD and the state of Texas, we're at the forefront of creating cutting-edge semiconductor manufacturing equipment and processes that will set the course for future advancements in semiconductor logic, memory, heterogeneous integration, chip cooling and more. Situated in the heart of Austin — named “America's Coolest City” by Expedia and “The Best Place to Live in the U.S.” by U.S. News and World Report — the Texas Institute for Electronics embodies the city's innovative spirit.
UT Austin, recognized by Forbes as one of America's Best Large Employers, provides outstanding employee benefits and total rewards packages that include:
Running, developing and integrating semiconductor fabrication processes across a wide variety of semiconductor equipment. This would include running experiments, performing detailed process characterization, performing data analysis, documentation of processes of record, presentation of results, and incorporating feedback from engineers/techs.
Developing processes-of-record and implementing these on product samples for customers.
Assisting with documents such as proposals or reports on costs and inventory levels.
High School Diploma or GED and at least ten years of experience in materials science, physics, chemistry, chemical engineering, electrical engineering, mechanical engineering, or other relevant disciplines, or, Bachelor's degree in materials science, physics, chemistry, chemical engineering, electrical engineering, mechanical engineering, or other relevant disciplines and at least six years of relevant experience in nanofabrication and exposure to wafer processing and characterization in cleanrooms, including experience working with standard semiconductor equipment for lithography, coating, plasma processes including deposition and etch, wet cleans, electroplating, annealing, chemical mechanical polishing, bonding, packaging, metrology and inspection.
Bachelor's degree in materials science, physics, chemistry, chemical engineering, electrical engineering, mechanical engineering, or other relevant disciplines and eight years of relevant experience in nanofabrication and exposure to wafer processing and characterization in cleanrooms, including experience working with standard semiconductor equipment for lithography, coating, plasma processes including deposition and etch, wet cleans, electroplating, annealing, chemical mechanical polishing, bonding, packaging, metrology and inspection, or, Master's degree in materials science, physics, chemistry, chemical engineering, electrical engineering, mechanical engineering, or other relevant disciplines and six years of relevant experience in nanofabrication and exposure to wafer processing and characterization in cleanrooms, including experience working with standard semiconductor equipment for lithography, coating, plasma processes including deposition and etch, wet cleans, electroplating, annealing, chemical mechanical polishing, bonding, packaging, metrology and inspection.
Bachelor's degree in materials science, physics, chemistry, chemical engineering, electrical engineering, mechanical engineering, or other relevant disciplines and ten years of experience in nanofabrication and exposure to wafer processing and characterization in cleanrooms, including experience working with standard semiconductor equipment for lithography, coating, plasma processes including deposition and etch, wet cleans, electroplating, annealing, chemical mechanical polishing, bonding, packaging, metrology and inspection, or Master's degree in materials science, physics, chemistry, chemical engineering, electrical engineering, mechanical engineering, or other relevant disciplines and eight years of relevant experience in nanofabrication and exposure to wafer processing and characterization in cleanrooms, including experience working with standard semiconductor equipment for lithography, coating, plasma processes including deposition and etch, wet cleans, electroplating, annealing, chemical mechanical polishing, bonding, packaging, metrology and inspection, or PhD in materials science, physics, chemistry, chemical engineering, electrical engineering, mechanical engineering, or another relevant discipline.
Goal-oriented and ability to prioritize and multitask.
Demonstrated excellent written and verbal communication skills.
Demonstrated ability to work successfully in a collaborative team environment.
Ability to work effectively in a dynamic and fast paced environment.
Three years of experience in nanofabrication and exposure to wafer processing and characterization in cleanrooms, including experience working with standard semiconductor equipment for lithography, coating, plasma processes including deposition and etch, wet cleans, electroplating, annealing, chemical mechanical polishing, bonding, packaging, metrology and inspection.
Master's degree or higher. Five or more years of relevant experience in nanofabrication and exposure to wafer processing and characterization in cleanrooms, including experience working with standard semiconductor equipment for lithography, coating, plasma processes including deposition and etch, wet cleans, electroplating, annealing, chemical mechanical polishing, bonding, packaging, metrology and inspection.
Master's degree or higher. Ten or more years of experience in nanofabrication and exposure to wafer processing and characterization in cleanrooms, including experience working with standard semiconductor equipment for lithography, coating, plasma processes including deposition and etch, wet cleans, electroplating, annealing, chemical mechanical polishing, bonding, packaging, metrology and inspection.
Experience working in a research or start-up environment.
Experience with programmatic layout creation software such as KLayout.
TIE pays industry-competitive salaries
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