Principal Signal Power Integrity Engineer, Texas Institute for Electronics Full-time

Principal Signal Power Integrity Engineer

The Texas Institute for Electronics (TIE) is a transformative, well-funded semiconductor foundry venture combining the agility of a startup with the scale of a national initiative.

A key part of our mission is to advance the state of the art in 3D heterogeneous integration (3DHI), chiplet-based architectures, and multi-component microsystems- catalyzing breakthroughs across microelectronics, artificial intelligence, quantum computing, high-performance computing, and next-generation healthcare devices.

Backed by $1.4 billion in combined funding from DARPA, Texas state initiatives, and strategic partners, we are building foundational capabilities in advanced packaging and integrated design infrastructure to restore U.S. leadership in microelectronics manufacturing.

Our 3DHI and chiplet integration platforms integrate novel thermal management and advanced interconnect solutions to deliver unprecedented performance and energy efficiency. Operating at the intersection of defense electronics and commercial markets, TIE offers a rare opportunity to reimagine an industry from the ground up and build transformative products with global impact.

UT Austin, recognized by Forbes as one of America's Best Large Employers, provides outstanding employee benefits and total rewards packages that include:

• Competitive health benefits (employee premiums covered at 100%, family premiums at 50%)
• Voluntary Vision, Dental, Life, and Disability insurance options
• Generous paid vacation, sick time, and holidays
• Teachers Retirement System of Texas, a defined benefit retirement plan, with employer matching funds
• Additional Voluntary Retirement Programs: Tax Sheltered Annuity 403(b) and a Deferred Compensation program 457(b)
• Flexible spending account options for medical and childcare expenses
• Robust free training access through LinkedIn Learning plus professional conference opportunities
• Tuition assistance
• Expansive employee discount program including athletic tickets
• Free access to UT Austin's libraries and museums with staff ID card
• Free rides on all UT Shuttle and Austin CapMetro buses with staff ID card

This role is to lead and execute comprehensive Signal Integrity (SI) and Power Integrity (PI) simulations for advanced 2.5D/3.0D heterogeneous integration and multi-material packages. The position will also collaborate with EDA vendors, OSATs, and foundries, and stay current with next-gen interface standards to guide technical strategy and mentor junior engineers.

• Own and drive signal integrity and power integrity (SI/PI) analysis end-to-end for advanced 2.5D/3.0D heterogeneous integration packages—from initial interconnect architecture through silicon-package co-design to final signoff.
• Perform high-speed interconnect modeling and extraction (S-parameters, RLCK, transmission-line models) across TSVs, micro-bumps, hybrid bonds, RDL, and advanced substrates (silicon, glass, organic).
• Architect and optimize power delivery networks (PDN) for multi-chiplet 3D stacks—including target impedance analysis, decoupling strategy, IR-drop simulation, and PDN resonance identification from die through package to board.
• Execute full SI simulation workflows: EM extraction, crosstalk analysis, eye diagram/BER prediction, channel compliance simulation, and jitter budgeting for high-speed interfaces (PCIe Gen6/7, CXL, UCIe, SerDes, HBM).
• Build and validate SI/PI models for the 3D Assembly Design Kit (ADK)—creating accurate, reusable electrical models that enable chiplet designers to perform system-level co-design against TIE's integration platform.
• Develop reference flows, scripts, and automation that make SI/PI enablement repeatable and accessible to internal design teams and external customers.
• Collaborate directly with EDA vendors (Cadence, Ansys, Synopsys, Siemens, Keysight), OSATs, and foundries to develop, benchmark, and refine package-level SI/PI simulation flows and tool interoperability.
• Track and incorporate requirements from next-gen interface standards (UCIe, PCIe, CXL, UALink, OIF-CEI, HBM) into package design rules and SI/PI methodology.
• Guide technical strategy for SI/PI at TIE, mentor engineers, and represent TIE in industry standards bodies, customer design reviews, and technical forums.

• BS in Electrical Engineering, Computer Engineering, Applied Physics, or related discipline.
• 12+ years of direct, hands-on experience in signal integrity and/or power integrity engineering for advanced packaging, 2.5D/3DIC, or heterogeneous integration platforms.
• Deep expertise with SI/PI and EM extraction tools: Ansys HFSS/SIwave, Cadence Sigrity/Clarity 3D, Synopsys RaptorX, Keysight ADS/PathWave, Siemens HyperLynx, or equivalent.
• Proven ability to build and deliver package-level electrical models (S-parameters, broadband RLCK, dielectric characterization) and integrate them into design enablement and signoff flows.
• Strong understanding of high-speed signaling fundamentals: transmission-line theory, impedance matching, return-path management, crosstalk mechanisms, ISI/jitter decomposition, and equalization techniques.
• Experience with PDN design methodology: target impedance, decap optimization, plane resonance, IR-drop analysis, and SSN/SSO mitigation in multi-die environments.
• Hands-on scripting and automation skills (Python, Tcl, SKILL, etc.) to streamline simulation and extraction flows.
• You're able to work with ambiguity, act with urgency, and take personal ownership for outcomes. Ability to make things happen.
• Execution mindset. You have demonstrated experience working in a hands-on role driving progress across multiple initiatives without layers of management.
• Location. Austin, Texas is preferred for close collaboration with our engineering teams and partners. Hybrid work arrangements may be possible, with travel up to 30–50% as needed. (Any flexible arrangement would be subject to university policies and approvals. Working outside of the state of Texas is subject to University review and approval in relation to jurisdictional employment and tax related laws, rules, and regulations.

• MS or PhD in Electrical Engineering, Applied Physics, or related discipline.
• Deep experience with multi-material package SI/PI challenges (Si interposers, glass substrates, organic build-up, Cu pillar/hybrid bond transitions) and their impact on signal loss, impedance control, and PDN performance.
• Demonstrated expertise in channel compliance and link-budget analysis for PCIe, CXL, UCIe, SerDes, or HBM, including silicon–package–board co-simulation.
• Familiarity with industry standards and working groups (IEEE, JEDEC, OIF, UCIe Consortium, 3Dblox, JEP30).
• Working knowledge of thermal and mechanical co-simulation and how thermo-mechanical effects (warpage, stress, CTE mismatch) influence SI/PI performance in 3D stacks.
• Experience creating or contributing to PDK/ADK simulation collateral for SI/PI design enablement.
• Track record of technical publications, patents, or open-source contributions in signal integrity, power integrity, or high-speed package design.

TIE Pays Industry-Competitive Salaries

• Repetitive use of a keyboard at a workstation
• Use of manual dexterity (ex: using a mouse)

• Monday – Friday 8am to 5pm
• Occasional/frequent nights/weekends required

• Resume/CV
• 3 work references with their contact information; at least one reference should be from a supervisor